View AD8323-15_8034592.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad8323 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 2000 5 v catv line driver fine step output power control functional block diagram diff or single input amp attenuation core z out diff = 75 8 8 8 z in (single) = 800 z in (diff) = 1.6k r1 r2 ad8323 daten data clk gnd (11 pins) pd sleep v out+ v out v cc (7 pins) v in+ v in buffer decode data latch shift register power-down logic power amp byp features supports docsis standard for reverse path transmission gain programmable in 0.75 db steps over a 53.5 db range low distortion at 60 dbmv output C56 dbc sfdr at 21 mhz C55 dbc sfdr at 42 mhz output noise level C48 dbmv in 160 khz maintains 75 output impedance power-up and power-down condition upper bandwidth: 100 mhz (full gain range) 5 v supply operation supports spi interfaces applications gain-programmable line driver hfc high-speed data modems interactive set-top boxes pc plug-in modems general-purpose digitally controlled variable gain block general description the ad8323 is a low-cost, digitally controlled, variable gain ampli- fier optimized for coaxial line driving applications such as cable modems that are designed to the mcns-docsis upstream standard. an 8-bit serial word determines the desired output gain over a 53.5 db range resulting in gain changes of 0.7526 db/lsb. the ad8323 comprises a digitally controlled variable attenuator of 0 db to ?3.5 db, which is preceded by a low noise, fixed gain buffer and is followed by a low distortion high power am- plifier. the ad8323 accepts a differential or single-ended input signal. the output is specified for driving a 75 ? load, such as coaxial cable. distortion performance of ?6 dbc is achieved with an output level up to 60 dbmv at 21 mhz bandwidth. a key performance and cost advantage of the ad8323 results from the ability to m ain- tain a constant 75 ? output impedance during power-up and power-down conditions. this eliminates the need for external 75 ? termination, resulting in twice the effective output voltage when compared to a standard operational amplifier. in addition, this device has a sleep mode function that reduces the quiescent current to 4 ma. the ad8323 is packaged in a low-cost 28-lead tssop, oper ates from a single 5 v supply, and has an operatio nal temperature range of ?0 c to +85 c. gain control dec code 50 0 distortion dbc 55 60 65 70 75 8 162432404856 hd3 hd2 f o = 42mhz p o = 60dbmv @ max gain 64 72 figure 1. harmonic distortion vs. gain control obsolete
rev. 0 C2C ad8323?pecifications (t a = 25 c, v s = 5 v, r l = r in = 75 , v in = 116 mv p-p, v out measured through a 1:1 transformer 1 with an insertion loss of 0.5 db @ 10 mhz unless otherwise noted.) parameter conditions min typ max unit input characteristics specified ac voltage output = 60 dbmv, max gain 116 mv p-p noise figure max gain, f = 10 mhz 13.8 db input resistance single-ended input 800 ? differential input 1600 ? input capacitance 2pf gain control interface gain range 52.5 53.5 54.5 db maximum gain gain code = 71 dec 26.5 27.5 28.5 db minimum gain gain code = 0 dec ?7 ?6 ?5 db gain scaling factor 0.7526 db/lsb output characteristics bandwidth (? db) all gain codes 100 mhz bandwidth roll-off f = 65 mhz 1.3 db bandwidth peaking f = 65 mhz 0 db output noise spectral density max gain, f = 10 mhz ?4 dbmv in 160 khz min gain, f = 10 mhz ?8 dbmv in 160 khz power-down mode, f = 10 mhz ?8 dbmv in 160 khz 1 db compression point max gain, f = 10 mhz 18.5 dbm differential output impedance power-up and power-down 75 20% ? overall performance second order harmonic distortion f = 21 mhz, p out = 60 dbmv @ max gain ?7 dbc f = 42 mhz, p out = 60 dbmv @ max gain ?1 dbc f = 65 mhz, p out = 60 dbmv @ max gain ?4 dbc third order harmonic distortion f = 21 mhz, p out = 60 dbmv @ max gain ?6 dbc f = 42 mhz, p out = 60 dbmv @ max gain ?5 dbc f = 65 mhz, p out = 60 dbmv @ max gain ?3 dbc gain linearity error f = 10 mhz, code to code 0.3 db output settling to 1 mv due to gain change min to max gain 60 ns due to input step change max gain, v in = 0 v to 116 mv p-p 30 ns signal feedthrough max gain, pd = 0, f = 42 mhz ?0 dbc power control power-up settling time to 1 mv max gain, v in = 0 300 ns power-down settling time to 1 mv max gain, v in = 0 40 ns between burst transients 2 equivalent output = 31 dbmv 3 mv p-p equivalent output = 60 dbmv 30 mv p-p power supply operating range 4.75 5 5.25 v quiescent current power-up mode 123 133 140 ma power-down mode 30 35 40 ma sleep mode 2 4 7 ma operating temperature ?0 +85 c range notes 1 toko 617db-a0070 used for above specifications. macom etc-1-it-15 can be substituted. 2 between burst transients measured at the output of a 42 mhz diplexer. specifications subject to change without notice. obsolete
rev. 0 ad8323 C3C logic inputs (ttl/cmos compatible logic) parameter min typ max unit logic ??voltage 2.1 5.0 v logic ??voltage 0 0.8 v logic ??current (v inh = 5 v) clk, sdata, daten 020na logic ??current (v inl = 0 v) clk, sdata, daten ?00 ?00 na logic ??current (v inh = 5 v) pd 50 190 a logic ??current (v inl = 0 v) pd ?50 ?0 a logic ??current (v inh = 5 v) sleep 50 190 a logic ??current (v inl = 0 v) sleep ?50 ?0 a timing requirements parameter min typ max unit clock pulsewidth (t wh ) 16.0 ns clock period (t c ) 32.0 ns setup time sdata vs. clock (t ds ) 5.0 ns setup time daten vs. clock (t es ) 15.0 ns hold time sdata vs. clock (t dh ) 5.0 ns hold time daten vs. clock (t eh ) 3.0 ns input rise and fall times, sdata, daten , clock (t r , t f )1 0 n s t es valid data word g1 msb. . . .lsb gain transfer (g1) t ds t eh 8 clock cycles gain transfer (g2) t off t gs analog output signal amplitude (p-p) pd pedestal clk sdata daten t on t c t wh valid data word g2 figure 2. serial interface timing valid data bit msb msb-1 msb-2 t ds t dh sdata clk figure 3. sdata timing (full temperature range, v cc = 5 v, t r = t f = 4 ns, f clk = 8 mhz unless otherwise noted.) ( daten , clk, sdata, pd , sleep , v cc = 5 v: full temperature range) obsolete
rev. 0 ad8323 C4C ordering guide model temperature range package description ja package option ad8323aru ?0 c to +85 c 28-lead tssop 67.7 c/w * ru-28 ad8323aru-reel 40 c to +85 c 28-lead tssop 67.7 c/w * ru-28 ad8323-eval evaluation board * thermal resistance measured on semi standard 4-layer board. absolute maximum ratings * supply voltage +v s pins 5, 9, 10, 19, 20, 23, 27 . . . . . . . . . . . . . . . . . . . . . . 6 v input voltages pins 25, 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 v pins 1, 2, 3, 6, 7 . . . . . . . . . . . . . . . . . . . . . ?.8 v to +5.5 v internal power dissipation tssop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.9 w operating temperature range . . . . . . . . . . . ?0 c to +85 c storage temperature range . . . . . . . . . . . . ?5 c to +150 c lead temperature, soldering 60 seconds . . . . . . . . . . . 300 c * stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. pin configuration top view (not to scale) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 ad8323 daten gnd sdata v cc clk v in gnd v in+ v cc gnd pd v cc sleep gnd gnd byp v cc v cc v cc v cc gnd gnd gnd gnd gnd gnd out out+ caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad8323 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device pin function descriptions pin no. mnemonic description 1 data enable low input. this port controls the 8-bit parallel data latch and shift register. a logic 0-to-1 transition transfers the latched data to the attenuator core (updates the gain) and simulta- neously inhibits serial data transfer into the register. a 1-to-0 transition inhibits the data latch (holds the previous gain state) and simultaneously enables the register for serial data load. 2 sdata serial data input. this digital input allows for an 8-bit serial (gain) word to be loaded into the internal register with the msb (most significant bit) first. 3 clk clock input. the clock port controls the serial attenuator data transfer rate to the 8-bit master- slave register. a logic 0-to-1 transition latches the data bit and a 1-to-0 transfers the data bit to the slave. this requires the input serial data word to be valid at or before this clock transition. 4, 8, 11,12, gnd common external ground reference. 13, 16, 17, 18, 22, 24, 28 5, 9, 10, 19, v cc common positive external supply voltage. a 0.1 f capacitor must decouple each pin. 20, 23, 27 6 logic ??powers down the part. logic ??powers up the part. 7 low power sleep mode. in the sleep mode, the ad8323? supply current is reduced to 4 ma. a logic ??powers down the part (high z out state) and a logic ??powers up the part. 14 out negative output signal. 15 out+ positive output signal. 21 byp internal bypass. this pin must be externally ac-coupled (0.1 f cap). 25 v in+ noninverting input. dc-biased to approximately v cc /2. for single-ended inverting operation, use a 0.1 f decoupling capacitor and a 39.2 ? resistor between v in+ and ground. 26 v in inverting input. dc-biased to approximately v cc /2. should be ac-coupled with a 0.1 f capacitor. obsolete
rev. 0 ad8323 C5C typical performance characteristics v cc out out+ v in+ v in gnd 82.5 v in out 1:1 0.1f 0.1f r ti 0.1f 0.1f 39.2 75 r l toko 617dba0070 tpc 1. basic test circuit gain control decimal gain error db 1.5 0 1.0 0.5 0.0 0.5 1.0 1.5 8 1624 32404856 f = 10mhz f = 5mhz f = 42mhz f = 65mhz 64 72 tpc 2. gain error vs. gain control frequency mhz gain db 40 0.1 30 20 10 0 10 20 30 40 1 10 100 1k 71d 46d 23d 00d tpc 3. ac response frequency mhz gain db 34 31 28 25 22 19 1 10 100 c l = 10pf c l = 20pf c l = 50pf in v in v in+ out c l 1:1 c l = 0pf p out = 60dbmv @ max gain 75 r l tpc 4. ac response for various cap loads gain control decimal output noise dbmv in 160khz 30 0 34 38 42 46 50 8 16 243240485664 72 f = 10mhz pd = 1 tpc 5. output referred noise vs. gain control frequency mhz feedthrough db 0 0.1 20 40 60 80 100 1 10 100 1k max gain min gain pd = 0 v in = 116mv p-p tpc 6. input signal feedthrough vs. frequency obsolete
rev. 0 ad8323 C6C fundamental frequency mhz distortion dbc 60 5 65 70 75 80 85 15 25 35 45 55 65 p out = 61dbmv @ max gain p out = 62dbmv @ max gain p out = 58dbmv @ max gain p out = 60dbmv @ max gain tpc 7. second order harmonic distortion vs. frequency for various output levels fundamental frequency mhz distortion dbc 5 45 50 55 60 65 15 25 35 45 55 65 p out = 60dbmv @ max gain p out = 58dbmv @ max gain p out = 62dbmv @ max gain p out = 61dbmv @ max gain tpc 8. third order harmonic distortion vs. frequency for various output levels frequency mhz p out dbmv 41.0 60 p out = 60dbmv @ max gain 41.4 41.8 42.2 42.6 43.0 40 20 0 40 50 30 10 10 20 30 41.2 41.6 42.0 42.4 42.8 tpc 9. two-tone intermodulation distortion frequency mhz impedance 85 1 10 100 80 75 70 65 60 55 r ti = 82.5 pd = 1 pd = 0 tpc 10. input impedance vs. frequency frequency mhz impedance 80 1 10 100 75 70 65 60 55 50 pd = 1 pd = 0 tpc 11. output impedance vs. frequency temperature c +i cc ma 140 50 100 90 80 70 60 50 40 30 20 25 0 25 50 75 100 pd = 1 pd = 0 130 120 110 tpc 12. supply current vs. temperature obsolete
rev. 0 ad8323 C7C applications general application the ad8323 is primarily intended for use as the upstream power amplifier (pa) in docsis (data over cable service interface specifications) certified cable modems and catv set- top boxes. upstream data is modulated in qpsk or qam for- mat, and done with dsp or a dedicated qpsk/qam m odulator. the amplifier receives its input signal from the qpsk/qam modulator or from a dac. in either case the signal must be low-pass filtered before being applied to the amplifier. because the distance from the cable modem to the central office will vary with each subscriber, the ad8323 must be capable of varying its output power by applying gain or attenuation to ensure that all signals arriving at the central office are of the same amplitude. the upstream signal path contains components such as a trans- former and diplexer that will result in some amount of power loss. therefore, the amplifier must be capable of providing enough power into a 75 ? load to overcome these losses without sacri- ficing the integrity of the output signal. operational description the ad8323 is composed of four analog functions in the power-up or forward mode. the input amplifier (preamp) can be used single-ended or differentially. if the input is used in the differential configuration, it is imperative that the input signals are 180 degrees out of phase and of equal amplitudes. this will en sure the proper gain accuracy and harmonic performance. the preamp stage drives a vernier stage that provides the fine tune gain adjustme nt. the 0.7526 db step resolution is implemented in this stage and provides a total of approximately 5.25 db of attenuation. after the vernier stage, a dac provides the bulk of the ad8323? attenuation (8 bits or 48 db). the signals in the preamp and vernier gain blocks are differential to improve the psrr and linearity. a differen- tial current is fed from the dac into the output stage, which amplifies these currents to the appropriate levels necessary to drive a 75 ? load. the output st age utilizes negative feed- back to implement a differential 75 ? output im pedance. this eliminates the need for external matching resistors needed in typical video (or video filter) termination requirements. spi programming and gain adjustment gain programming of the ad8323 is accomplished using a serial peripheral interface (spi) and three digital control lines, daten , sdata, and clk. to change the gain, eight bits of data are streamed into the serial shift register through the sdata port. the sdata load sequence begins with a falling edge on the daten pin, thus activating the clk line. although the clk line is now activated, no change in gain is yet observed at the output of the amplifier. with the clk line activated, data on the sdata line is clocked into the serial shift register most significant bit (msb) first, on the rising edge of each clk pulse. because only a 7-bit shift register is used, the msb of the 8-bit word is a ?on? care?bit and is shifted out of the register on the eighth clock pulse. a rising edge on the daten line latches the contents of the shift register into the attenuator core resulting in a well controlled change in the output signal level. the serial interface timing for the ad8323 is shown in figures 2 and 3. the programmable gain range of the ad8323 is ?6 db to +27.5 db and scales 0.7526 db per least significant bit (lsb). because the ad8323 was characterized with a toko transformer, the stated gain values already take into account the losses associ- ated with the transformer. the gain transfer function is as follows: a v = 27.5 db ?(0.7526 db (71 ?code) ) for 0 code 71 where a v is the gain in db and code is the decimal equivalent of the 8-bit word. valid gain codes are from 0 to 71. figure 4 shows the gain characteristics of the ad8323 for all possible values in an 8-bit word. note that maximum gain is achieved at code 71. from code 72 through 127 the 5.25 db of attenuation from the ver- nier stage is being applied over every eight codes, resulting in the sawtooth characteristic at the top of the gain range. because the eighth bit is a ?on? care?bit, the characteristic for codes 0 through 127 repeats from codes 128 through 255. gain code decimal 7 0 gain db 0 7 14 21 28 32 64 96 128 160 192 224 28 14 21 256 figure 4. gain vs. gain code input bias, impedance, and termination the v in+ and v in inputs have a dc bias level of approximately v cc /2, there fore the input signal should be ac-coupled. the differential input impedance is approximately 1600 ? while the single-ended input impedance is 800 ? . if the ad8323 is being operated in a single-ended input configuration with a desired input impedance of 75 ? , the v in+ and v in inputs should be terminated as shown in figure 5. if an input impedance other than 75 ? is desired, the values of r1 and r2 in figure 5 can be calculated using the following equations: zr in = 1 800 rzr in 21 = z in = 75 ad8323 r1 = 82.5 r2 = 39.2 + figure 5. single-ended input termination obsolete
rev. 0 ad8323 C8C output bias, impedance, and termination the differential output pins v out+ and v out are also biased to a dc level of approximately v cc /2. therefore, the outputs should be ac-coupled before being applied to the load. this may be accomplished by connecting 0.1 f capacitors in series with the outputs as shown in the typical applications circuit of figure 6. the differential output impedance of the ad8323 is internally maint ained at 75 ? , regardless of whether the amplifier is in forward transmit mode or reverse power-down mode, elimi- nating the need for external back termination resistors. a 1:1 transformer (toko #617db-a0070) is used to couple the amplifier s differential output to the coaxial cable while maintaining a proper impedance match. if the output signal is being evaluated on standard 50 ? test equipment, a 75 ? to 50 ? pad must be used to provide the test circuit with the correct impedance match. power supply decoupling, grounding, and layout consid erations careful attention to printed circuit board layout details will prevent problems due to associated bo ard parasitics. proper rf design technique is mandatory. the 5 v supply power should be delivered to each of the v cc pins via a low impe dance power bus to ensure that each pin is at the same potential. the power bus should be decoupled to ground with a 10 f tantalum capacitor located in close proximity to the ad8323. in addition to the 10 f capacitor, each v cc pin should be individually decoupled to ground with a 0.1 f ceramic chip capacitor located as close to the pin as possible. the pin labeled byp (pin 21) should also be decoupled with a 0.1 f capacitor. the pcb should have a low- impedance ground plane covering all unused porti ons of the component side of the board, except in the area of the input and output tr aces (see figure 11). it is impo rtant that all of the ad8323 s ground pins are connected to the ground plane to ensure proper grounding of all internal nodes. the differential input and output traces should be kept as short and symmetrical as possible. in addition, the input and output traces should be kept far apart in order to minimize coupling (crosstalk) through the board. following these guidelines will improve the overall performance of the ad8323 in all applications. initial power-up when the 5 v supply is first applied to the v cc pins of the ad8323, the gain setting of the amplifier is indeterminate. therefore, as power is first applied to the amplifier, the pd pin should be held low (logic 0) thus preventing forward signal transmission. after power has been applied to the amplifier, the gain can be set to the desired level by following the procedure in the spi programming and gain adjustment section. the pd pin can then be brought from logic 0 to 1, enabling forward signal transmission at the desired gain level. asynchronous power-down the asynchronous pd pin is used to place the ad8323 into between burst mode while maintaining a differential output impedance of 75 ? . applying a logic 0 to the pd pin activates the on-chip reverse amplifier, providing a 74% reduction in consumed power. the supply current is reduced from approxi- mately 133 ma to approximately 35 ma. in this mode of operation, between burst noise is minimized and the amplifier can no longer transmit in the upstream direction. in addition to the pd pin, the ad8323 also incorporates an asynchronous sleep pin, which may be used to place the amplifier in a high output impedance state and further reduce the supply current to approximately 4 ma. applying a logic 0 to the sleep pin places the amplifier into sleep mode. transitioning into or out of sleep mode will result in a transient voltage at the output of the amplifier. therefore, use only the pd pin for docsis compliant between burst operation. daten sdata clk gnd1 v cc pd sleep gnd2 v cc 1 v cc2 gnd3 gnd4 gnd5 out gnd11 v cc6 v in v in+ gnd10 v cc5 gnd9 byp v cc4 v cc3 gnd8 gnd7 gnd6 out+ ad8323tssop 5v pd sleep daten sdata clk 10f 25v 0.1f 0.1f 0.1f 0.1f 0.1f toko 617db-a0070 to diplexer z in = 75 0.1f 0.1f 0.1f 0.1f 0.1f 0.1f 0.1f 165 v in v in+ z in = 150 figure 6. typical applications circuit obsolete
rev. 0 ad8323 C9C distortion, adjacent channel power, and docsis in order to deliver 58 dbmv of high fidelity output power required by docsis, the pa should be able to deliver about 60 dbmv to 61 dbmv in order to make up for losses associated with the transformer and diplexer. it should be noted that the ad8323 was characterized with the toko 617db-a0070 transformer. tpc 7 and tpc 8 show the ad8323 second and third harmonic distortion performance versus fundamental frequency for various output power levels. these figures are useful for determining the inband harmonic levels from 5 mhz to 65 mhz. harmonics higher in frequency will be sharply attenu- ated by the low-pass filter function of the diplexer. another measure of signal integrity is adjacent channel power or acp. docsis section 4.2.9.1.1 states, spurious emissions from a transmitted carrier may occur in an adjacent channel that could be occupied by a carrier of the same or different symbol r ates. figure 7 shows the measured acp for a 16 qam, 60 dbmv signal, taken at the output of the ad8323 evaluation board (see figure 13 for evaluation board schematic). the transmit chan- nel width and adjacent channel width in figure 7 correspond to symbol rates of 160 k sym/sec . table i shows the acp results for the ad8323 for all conditions in docsis table 4-7 adjacent channel spurious emissions. 10 20 30 40 70 50 60 80 center 10 mhz 60 khz span 600 khz cl1 c0 c0 cu1 cl1 rbw 500 hz rf att 40db vbw 5 khz swt 12s unit dbm ch pwr 5.44 dbm acp up 52.99 db acp low 54.36 db f1 cu1 figure 7. adjacent channel power table i. acp performance for all docsis conditions (all values in dbc) transmit channel symbol rate 160 k sym/sec 320 k sym/sec 640 k sym/sec 1280 k sym/sec 2560 k sym/sec 53.0 160 k sym/sec 320 k sym/sec 640 k sym/sec 1280 k sym/sec 2560 k sym/sec adjacent channel symbol rate 53.8 55.0 56.6 56.3 52.7 53.4 53.8 54.8 55.4 53.8 52.9 53.3 53.6 54.2 53.7 53.4 53.0 53.3 53.5 55.4 54.0 53.6 53.1 53.3 noise and docsis at minimum gain, the ad8323 s output noise spectral density is 10 nv/ hz measured at 10 mhz. docsis table 4-8, spurious emissions in 5 mhz to 42 mhz, specifies the output noise for various symbol rates. the calculated noise power in dbmv for 160 k sym/second is: 20 10 160 60 48 2 log nv hz khz dbmv ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? += comparing the computed noise power of 48 dbmv to the 8 dbmv signal yields 56 dbc, which meets the required level of 53 dbc set forth in docsis table 4-8. as the ad8323 s gain is increased from this minimum value, the output signal increases at a faster rate than the noise, resulting in a signal to noise ratio that improves with gain. in transmit disable mode, the output noise spectral density computed over 160 k sym/second is 1.0 nv/ hz or 68 dbmv. evaluation board features and operation the ad8323 evaluation board (part # ad8323-eval) and control software can be used to control the ad8323 upstream cable driver via the parallel port of a pc. a standard printer cable connected between the parallel port and the evaluation board is used to feed all the n ecessary data to the ad8323 by means of the windows-based, microsoft visual basic control software. this package provides a means of evaluating the amplifier by providing a convenient way to program the gain/ attenuation as well as offering easy control of the amplifiers asyn chronous pd and sleep pins. with this evaluation kit the ad8323 can be evaluated with either a single-ended or differential input configuration. the amplifier can also be evaluated with or without the pulse diplexer in the output signal path. to remove the diplexer from the signal path, move the 0 ? chip resistor at jp5 so the output signal is directed away from the diplexer and toward the cable port of the evaluation board. also, remove the 0 ? resistor at jp4. a schematic of the evaluation board is provided in figure 13. overshoot on pc printer ports the data lines on some pc parallel printer ports have excessive overshoot that may cause communications problems when pre- sented to the clk pin of the ad8323 (tp5 on the evaluation board). the evaluation board was designed to accommodate a series resistor and shunt capacitor (r1 and c15) to filter the clk signal if required. transformer and diplexer a 1:1 transformer is needed to couple the differential outputs of the ad8323 to the cable while maintaining a proper impedance match. the specified transformer is available from toko (part # 617db-a0070); however, ma/com part # etc-1-1t-15 can also be used. the evaluation board is equipped with the toko transf ormer, but is also designed to accept the ma/ com transformer. the pulse diplexer included on the evalu ation board provides a high-order low-pass filter function, typically used in the upstream path. the ability of the pulse diplexer to achieve docsis compliance is neither expressed nor im plied by analog devices inc. data on the diplexer should be obtained from pulse. differential inputs the ad8323-eval evaluation board is designed to accommo date a mini-circuits t1-6t-kk81 1:1 transformer for the purpose of converting a single-ended (ground-referenced) input signal to differential inputs. figure 8 and the following paragraphs iden tify two options for providing differential input signals to the ad 8323 evaluation board. obsolete
rev. 0 ad8323 C10C single-ended-to-differential input (figure 8, option 1) install the mini-circuits t1-6t-kk81 1:1 transformer in the t1 location of the evaluation board. place 0 ? chip resistors at locations jp1, jp2, and jp3 such that the signal coming in v in+ is directed toward the transformer and the differential signal coming out of the transformer is directed toward tp13 and tp14. for 75 ? input impedance, install 39.2 ? resistors in r5 and r6 located on the back side of the evaluation board. in this configuration the input signal must be applied to the v in+ port of the evaluation board from a single-ended 75 ? signal source. for input impedances other than 75 ? , the correct value for r5 and r6 can be computed using the following equation: r r r desired pedance r 5 6 2 800 == () = () , im differential input (figure 8, option 2) if a differential signal source is available, it may be applied directly to both the v in+ and v in input ports of the evaluation board. in this case, 0 ? chip resistors should be placed at loca- tions r8, jp1, jp2, and jp3 such that the v in+ and v in signals are directed toward tp13 and tp14. referring to figure 8, option 2, a differential input impedance of 150 ? can be achieved by using a 165 ? resistor for r7. for input imped- ances other than 150 ? , the correct value for r7 can be com puted using the following equation: desired pedance r im = () 7 1600 diff in t1 r5 r6 ad8323 vin+ ad8323 option 1 differential input termination option 2 differential input termination vin r7 figure 8. differential input termination options installing the visual basic control software to install the cabdrive_23 evaluation board control soft- ware, close all windows applications and then run setup.exe located on disk 1 of the ad8323 evaluation software. follow the on-screen instructions and insert disk 2 when prompted to do so. enter the path of the directory into which the software will be installed and select the button in the upper left corner to complete the installation. running the software to invoke the control software, go to start -> programs -> cabdrive_23, or select the ad8323.exe icon from the directory containing the software. controlling the gain/attenuation of the ad8323 the slide bar controls the ad8323 s gain/attenuation, which is displayed in db and in v/v. the gain scales at 0.7526 db per lsb with the valid codes being from decimal 0 to 71. the gain code (i.e., position of the slide bar) is displayed in decimal, binary, and hexadecimal (see figure 9). power-up, power-down and sleep the power-up and power-down buttons select the mode of operation of the ad8323 by controlling the logic level on the asynchronous pd pin. the power-up button applies a logic 1 to the pd pin putting the ad8323 in forward transmit mode. the power-down button applies a logic 0 to the pd pin selecting reverse mode, where the forward signal transmission is disabled while a back termination of 75 ? is maintained. checking the enable sleep mode box applies a logic 0 to the asynchronous sleep pin, putting the ad8323 into sleep mode. memory section the memory section of the software provides a convenient way to alternate between two gain settings. the x->m1 but- ton stores the current value of the gain slide bar into memory while the rm1 button recalls the stored value, returning the gain slide bar to that level. the x->m2 and rm2 buttons work in the same manner. obsolete
rev. 0 ad8323 C11C evaluation board features and operation figure 9. screen display of windows-based control software obsolete
rev. 0 ad8323 C12C figure 10. evaluation boardassembly (component side) figure 11. evaluation board layout (component side) obsolete
rev. 0 ad8323 C13C figure 12. evaluation boardsolder side obsolete
rev. 0 ad8323 C14C nc = 5 t1 dni 1:1 nc = 2 t2b 1:1 t2a dni 1:1 daten sdata clk gnd1 v cc pd sleep gnd2 v cc1 v cc2 gnd3 gnd4 gnd5 out gnd11 v cc6 v in v in+ gnd10 v cc5 gnd9 byp v cc4 v cc3 gnd8 gnd7 gnd6 out+ u1 ad8323tssop 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 0.1f 0.1f 0.1f 0.1f 0.1f c8 c7 c6 c5 c2 c13 0.1f c12 0.1f r5 82.5 r6 39.2 r7 dni tp14 yel tp13 yel a b b aa b 4 6 3 1 2 1 2 3 3 1 2 1 2 3 r8 0 r9 dni v in v in+ s2 s3 agnd;3,4,5 agnd;3,4,5 g1 g2 g3 g4 g5 g6 g7 g8 g9 18 17 16 15 14 13 12 11 10 pulseb5008 out = 2,4,6,7,8 a ab b u2 agnd;3,4,5 agnd;3,4,5 s4 s1 tp21 dni tp22 dni 1 3 5 9 tp10 dni jp4 jp5 jp1 jp3 jp2 2 1 3 a b r4 dni r3 0 cable hpp tp9 dni tp11 dni tp12 dni c11 0.1f toko-b4f etcc1-1t 4 3 4 5 5 1 3 1 2 tp8 dni tp7 dni c10 0.1f tp4 tp6 r2 0 wht wht pd c14 dni tp2 tp5 r1 0 wht wht clk tp16 c15 dni c16 dni c17 dni tp17 r11 0 wht wht sleep tp19 r12 0 wht wht spare tp18 tp1 wht sdata tp3 wht daten p1 p1 p1 p1 p1 p1 p1 p1 p1 p1 p1 p1 p1 p1 p1 p1 p1 p1 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 p1 p1 p1 p1 p1 p1 p1 p1 p1 p1 p1 p1 p1 p1 p1 p1 p1 p1 amp-552742 v cc j1 j2 agnd blk tp20 c18 10f 25v tp15 red + 1 1 daten sdata clk pd sleep c1 0.1f c3 0.1f c4 0.1f figure 13. evaluation board schematic obsolete
rev. 0 ad8323 C15C evaluation board bill of materials ad8323 evaluation board rev. c single-ended inverting input revised june 22, 2000 qty. description vendor ref desc. 1 10 f 16 v. c size tantalum chip capacitor ads# 4-7-6 c18 12 0.1 f 50 v. 1206 size ceramic chip capacitor ads# 4-5-18 c1 8, 10 13 60 ? 1/8 w. 1206 size chip resistor ads# 3-18- 88 r1 3, 8, 11, 12 1 39.2 ? 1% 1/8 w. 1206 size chip resistor ads# 3-18-113 r6 1 82.5 ? 1% 1/8 w. 1206 size chip resistor ads# 3-18-189 r5 2 yellow test point [inputs] (bisco tp104-01-04) ads# 12-18-32 tp13, 14 10 white test point [data] (bisco tp104-01-09) ads# 12-18-42 tp1 6, 16 19 1 red test point [v cc ] (bisco tp104-01-02) ads# 12-18-43 tp15 1 black test point [a.gnd] (bisco tp104-01-00) ads# 12-18-44 tp20 30 ? 0805 size chip resistors ads# 3-27-22 jp1 3 475 ? right-angle bnc telegartner # j01003a1949 ads# 12-6-28 vin+, vin , hpp, cable 1 centronics type 36 pin right-angle connector ads# 12-3-50 p1 2 5-way metal binding post (e f johnson # 111-2223-001) ads# 12-7-7 vcc, gnd 1 1:1 transformer toko # 617db - a0070 toko t2 b 1 diplexer pulse * pulse u2 1 ad8323 (tssop) upstream cable driver adi# ad8323xru u1 1 ad8323 rev. c evaluation pc board d c s evaluation pc board 4 #4 - 40 1/4 inch stainless panhead machine screw ads# 30-1-1 4 #4 - 40 3/4 inch long aluminum round stand-off ads# 30-16-3 2 # 2 - 56 3/8 inch stainless panhead machine screw ads# 30-1-17 (p1 hardware) 2 # 2 steel flat washer ads# 30-6-6 (p1 hardware) 2 # 2 steel internal tooth lockwasher ads# 30-5-2 (p1 hardware) 3 # 2 stainless steel hex. machine nut ads# 30-7-6 (p1 hardware) do not install c14 c17, r4, r7, r9, t1, t2a, tp7 tp12, tp21, tp22. * pulse diplexer part # s b5008 (42 mhz), cx6002 (42 mhz), b5009 (65 mhz). obsolete
rev. 0 C16C c02045C2.5C7/00 (rev. 0) printed in u.s.a. ad8323 outline dimensions dimensions shown in inches and (mm). 28-lead tssop (ru-28) 0.177 (4.50) 0.169 (4.30) 28 15 14 1 0.386 (9.80) 0.378 (9.60) 0.256 (6.50) 0.246 (6.25) pin 1 seating plane 0.006 (0.15) 0.002 (0.05) 0.0118 (0.30) 0.0075 (0.19) 0.0256 (0.65) bsc 0.0433 (1.10) max 0.0079 (0.20) 0.0035 (0.090) 0.028 (0.70) 0.020 (0.50) 8 0 obsolete

▲Up To Search▲

Price & Availability of AD8323-15

	To Download AD8323-15 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .